Latest Answer: In transmission its considered as download and upload
so, we have 64kbps
Divide by 8 to get the download speed so its 8kbps ie 8192 bits per sec
Now consider the image its 540Bytes convert into bits its 540*1024 = 552960
So divide both 552960 ...
Latest Answer: 512 adresses and 4 bit word. Hence 2048 bits. ...
Latest Answer: requires 16 bits , but we need 16 only when 2 input's are max(2^8-1),since nothing has been specified we need 16 bits ...
Latest Answer: could be anywhere in memory. You can get the address from the location in IVT (assuming this subroutine is not chained) based on service number (i.e Interrupt no)location of address (i.e pointer)is available at 4*(interrupt serviced) ...
Latest Answer: actually question is about controller ,controller first aserts intr signal then after receiving intra continues the communication ...
Latest Answer: 003c ...
Latest Answer: ANS: FA3H:: msb remains same. retst is obtained by xoring the consecutive bits. ...
An active HIGH input S-R latch has a 1 on the S input and a 0 on the R input. What state is the latch in?
Latest Answer: First of all understand the question correctly,what is parity generation? not why parity generation?Ans :parity generation is generation of code word according to number of 1's present in that particular word,(example:10001010 for odd:0 or for even:1) ...
Suppose that the D input of a flip flop changes from low to high in the middle of a clock pulse. Describe what happens if the flip flop is a positive edge triggered type?
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