What is the race around condition? How can it be overcome?

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K.Hari Kishore

  • Jun 16th, 2005

Hi this is har. Race conditions is a severe way crashing the server/ system at times. Generally this problem arises in priority less systems or the users who has eqal priority will be put to this problem. Race condition is a situation in which a resource D is to be serviced to a process A and the processB which holds the resoure C is to be given to the process A. So a cyclic chain occurs and no way the resources will be get shared and also the systems with equal prirority wont get the resoure so that the system wont come out of the blocked state due to race condition!

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  • Jul 19th, 2011

when we put j=1 and k=1 in j-k flip flop, the output, Q
toggles to 0 and 1 continuously; and it becomes uncertain to predict the output. This condition is known as Race around condition. It can be rectified using Master-Slave flip flop.

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  • Oct 29th, 2011

after applying the clock the output must be changed only once, but it change continuously until the clock remains 1. this condition is called as race around condition. it can be eliminated by J-K master slave configuration.

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  • Nov 20th, 2012

in JK flip flop when both inputs are high (J & K) the output switches between 1 and 0 (toggle condition) continuously. this is known as race around condition.

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rhuturaj mishra

  • May 20th, 2014

i guess ur answer is wrong....since there is no race around in SR filp flop but in JK.....in fact S=1 and R=1 condition in SR flip flop is a prohibited or not allowed condition

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  • Aug 17th, 2014

Race around condition arises in J-K flip flop when both J=K=1 & it can be overcome by using master slave JK flip flops.

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pradip rathod

  • Nov 30th, 2014

When j=k=1, & clock pulse is applied as the clock I/p.
at the end of clock pulse, the value of Q is uncertain, this situation is referred to as race around condition.

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  • May 19th, 2015

it can be overcome by using master slave jk flip flop and by using the edge triggered jk flip flop.

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Consider active high JK Latch. Here JK latch is enabled when enable is high. When enable is high, and when J and K are 1, output toggles. It will toggle as long as your enable is asserted and J and K are 1 ( 0 -> 1 -> 0 -> 1 so on). As the result output becomes uncertain. To solve this issue, minimize the asserted period of the enable (practically speaking, use edge triggered flip-flop).

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Abhinay Singh

  • Aug 12th, 2015

A race around condition defined a undesirable state in digital circuit of flip flop. It can be avoid by using master slave flipflop.

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  • Nov 3rd, 2015

It is all about j-k Flip Flop. When the two inputs are high, the output is unpredictable as it toggles between 0 & 1, it is called race around condition.

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  • Jan 13th, 2016

Practically, We dont get toggling since clock pulse is more than the propagation delay. so within one clock pulse, the output will keep on toggling again and again and it may become indeterminate. this is known as Race Around Conditions.
It can be rectified by using Master Slave Flipflop.

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  • May 12th, 2016

A race around condition defined a undesirable state in digital circuit of flip flop. It can be avoid by using master slave flipflop.

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  • Oct 19th, 2016

Race around condition occur in a jk flipflop. In this flipflop the output of second goes as the input to the first nand gate ie J also while the first output goes as input for second ie K so when after certain clocks it becomes a confusing state whether to accept this output or other output for the JK inputs. This condition is basically race around condition..
It can be avoided by using Master Slave FF or Edge triggered FF.

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  • Nov 17th, 2016

In JK filpflop, j=1,k=1,clk at logic high then the flip-flop is in toggle case it leads to race around condition it can be by using JK master slave filpflop

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