Race Around Condition

What is Race Around Condition in a JK FlipFlop? How it can be avoided?

Questions by ANANDM.M4   answers by ANANDM.M4

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  • Jun 24th, 2009

IN J-K FF , The clock time is higher than the output toggling time then for J=1 & K=1 , the output will be changed irrelavent of our input. This condition is known as "RACE AROUND CONDITION".

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  • Feb 15th, 2010

When the input to the JK flip-flop is j=1 and k=1, the race around condition occurs, i.e it occurs when the time period of the clock pulse is greater than the propagation delay of the flip flop. so the output changes or toggles in a single clock period. If it toggles even number of times the output is same but if it toggles odd number of times then the output is complimented. To avoid race around condition we cant make the clock pulse smaller than the propagation delay so we use
1. Master slave JK flip flop
2. Positive or negative edge triggering
Since the hardware cost of msjk is more edge triggering is preferred to msjk.


  • Oct 7th, 2010

In SR flip flop Race condition occurs when both S=r=1..i.e both the outputs Q andQbar race to the same level..this is called race condition...IN JK flipflop whwn J=k=1 the outputs RAce around 0 and 1..the output of the circuit will be 0-->1-->0-->1..when both the J and k are high it can be used as Toggle flipflop

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ram choudhary

  • Oct 6th, 2014

race around condition is the disadvantage of jk flip flop. when flip flop delay is less than the pulse width of clock. and also during race around flip flop output changes multiple times in single clock.

To avoid race around flip flop delay must be greater than pulse width of the clock. or we can use master slave flip flop.

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  • Oct 26th, 2015

Thanks a lot. You made it easy to understand.

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Ahmad Bashar

  • Dec 31st, 2015

Race around condition is a disadvantage of JK FF in which the output changes multiple times in a single clock pulse, because the FF delay is less than the clock pulse width.

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Sanju rawat

  • Jul 5th, 2016

In J K F/F, if J=K=1, then output will be unstable
"1 to 0 OR 0 to 1"
This called race around condition.

This condition may be start when
Pulse width > propagation delay of J K F/F ..

for finish that we have to use Master slave F/F ..

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Pooja poddar

  • Oct 24th, 2016

When the input to JK flip-flop is j=1 and k=1 it is called race around condition
Two ways to avoid it are
1) Masters key
2) Use edge triggered JK flip flop

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Pulkit Aggarwal

  • Apr 14th, 2017

When J=K=1 and Q=0 and clock input is applied after a time interval 🔺t equal to propagation delay, output Q=1. Now, we have J=K=Q=1 and after another time interval 🔺t output changes back to Q=0 .i.e. output oscillates between 0 & 1. At the end of clock pulse, output becomes uncertain. This situation is referred as RACE AROUND CONDITION.
The race around condition can be avoided if tp 《 🔺t 《 T

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Arindam Nag

  • May 14th, 2017

It can be overcome when clock pulse will be over.clk=0

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