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![]() Related Questions On-line information system provides 1. users with immediate access to all the files for interrogration 2. users to do initial amendment or updation of files initially 3. processing of periodically collected data in group at specific intervals 4. the usage of separated and not connected data with the main computer Which of the following is not an input device 1. MICR 2. OCR 3. DVD 4. JOYSTICK Latest Answer : But I think it is DVD ... If the input J is connected through K input of J-K flip-flop, the flip-flop will behave as a 1. D(Delay) type flip-flop 2. T-type flip-flop 3. Toggle Switch 4. 2 or 3 above Latest Answer : D- flip flop ... If a clock with time period 'T' is used with 'n' stage shift register, the output of the final stage will be delayed by 1. nT seconds 2. (n-1)T seconds Latest Answer : nT seconds ... In a ripple counter using edge-triggered JK flip-flop. the pulse input is applied to the 1. clock input of oll flip-flops 2. clock input of one flip-flop 3. J and K input of Latest Answer : clock input of one flipflop ... in a ripple counter using edge-triggered JK flip-flop. the pulse input is applied to the 1. clock input of oll flip-flops 2. clock input of one flip-flop 3. J and K input of one Latest Answer : clock input of one flipflop ... The output of the lexical analyser is 1. a set of regular expressions 2. syntax tree 3. set of tokens 4. string of characters Design a digital circuit which has one input two output and one select lineinput should be 1000khzoutput should be 500khz and 250Khzselect line either 0 or 1if 0 select 250khz if 1 select 500khz Latest Answer : In OPAMP, we have 4 stages, 1st stage, i.e the input stage is a dual i/p balanced o/p opamp whose i/p resistance is v high. and if we use FET in case of BJT for 1st stage diffamp, then i/p resistance will be v high in M ohms. ... Read Answers (1) | Asked by : naveen.s.h Why the input resistance of an ideal OP-AMP is infinite and output resistance is zero?secondly, how can we measure these resistances(input and output) in case of an ideal OP-AMP and Real OP-AMP in the following conditions when 1- load is not connected. 2- load is connected.
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