How many characters per sec (7 bits + 1 parity ) can be transmitted over a 2400 bps line if the transfer is synchronous (1 start and 1 stop bit)? 1. 300 2. 240 3. 250 4. 275
The number of columns in a state table for a sequential circuit with m flip-flops and n inputs is 1. m + n 2. m + 2n 3. 2m + n 4. 2m + 2n
The output of the lexical analyser is 1. a set of regular expressions 2. syntax tree 3. set of tokens 4. string of characters
The Answer is Certified European
Latest Answer: The CE mark is a mandatory European marking for certain product groups to indicate conformity with the essential health and safety requirements set out in European Directives. The letters 'CE' are an abbreviation of Conformité Européenne, ...
which of the following architectures is/are not suitable for realizing SIMD ? 1. vector processor 2. array processor 3. von neumann 4. both array processor and von neumann
in a ripple counter using edge-triggered JK flip-flop. the pulse input is applied to the 1. clock input of oll flip-flops 2. clock input of one flip-flop 3. J and K input of one
Latest Answer: clock input of one flipflop ...
In a ripple counter using edge-triggered JK flip-flop. the pulse input is applied to the 1. clock input of oll flip-flops 2. clock input of one flip-flop 3. J and K input of
Latest Answer: clock input of one flipflop ...
Motorola's 68040 is comparable to 1. 8085 2. 80286 3. 80386 4. 80486
Latest Answer: the answer is 80486 ...
If a clock with time period 'T' is used with 'n' stage shift register, the output of the final stage will be delayed by 1. nT seconds 2. (n-1)T seconds
Latest Answer: nT seconds ...
If the input J is connected through K input of J-K flip-flop, the flip-flop will behave as a 1. D(Delay) type flip-flop 2. T-type flip-flop 3. Toggle Switch 4. 2 or 3 above
Latest Answer: D- flip flop ...
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