Structure Padding in C

Let us assume that a structure in C is declared as below:

struct aaa {
int a;
char b;
int c;
}

Assuming that I am running on a 32-bit machine, can I assume that the size of the structure is 9 bytes?? If not why not??

I will wait sometime before posting the answer.

Not really sure what you are expecting as answer, but rather than the machine you run, it is the compiler that matters. Like if you are runnning a 16 bit compiler on on 32 bit machine, the size of your struct will just be 5 bytes.

-Kalayama

It's not only compiler ...
The simple answer is compilers pad structures to optimize data transfers. This is an hardware architecture issue. Most modern CPUs perform best when fundemental types, like 'int' or 'float', are algined on memory boundarys of a particular size (eg. often a 4byte word on 32bit archs). Many architectures don't allow misaligned access or if they do inccur a performance penalty.

[QUOTE=konark;23364]It's not only compiler ...
The simple answer is compilers pad structures to optimize data transfers. This is an hardware architecture issue. Most modern CPUs perform best when fundemental types, like 'int' or 'float', are algined on memory boundarys of a particular size (eg. often a 4byte word on 32bit archs). Many architectures don't allow misaligned access or if they do inccur a performance penalty.[/QUOTE]

Wonderful. This is exactly the discussion I wanted to have.

So, yes.
- As Kalayama said, depending on the compiler (16 or 32 or 64bit), the padding size differs. But, why have padding at all??
- And, as Konark said, there is a hardware alignment issue. If the memory accesses are not aligned to a word boundary, there is a performance penalty.

But, here is the important question: what is the performance penalty?? In the example I gave listed below:

struct aaa {
int a;
char b;
int c;
}

What if the compiler did not pad the structure?? What is the penalty?? Can we discuss this?? I feel it would be useful to understand this: really understand this.

Hello,

First to answer the Size of the structure which u have mentioned would be listed is 12bytes on 32bit compiler and on 16bit it would be 6bytes.

Now Reason as already mentioned is because of the Structure Padding. And padding is for the Memory allignment.

Now
What if the compiler did not pad the structure?? What is the penalty?? Can we discuss this??

What if the compiler did not pad the structure?
If compiler does not pad the structure the memory access complexity would be high. Padding makes sure of the address alignment,
1. As you know the size of pointer is 4 bytes.
So, if everything is organized by a multiple of 4, then it will be
easier and faster to calculate the addresses and processing
them.
2. Address allignment does also makes read and write faster

The reasons for not permitting misaligned long word reads and writes are not difficult to see. For example, an aligned long word X would be written as X0, X1, X2 and X3. Thus the microprocessor can read the complete long word in a single bus cycle. If the same microprocessor now attempts to access a long word at address 0x000D, it will have to read bytes Y0, Y1, Y2 and Y3. Notice that this read cannot be performed in a single 32 bit bus cycle. The microprocessor will have to issue two different reads at address 0x100C and 0x1010 to read the complete long word. Thus it takes twice the time to read a misaligned long word.
Byte 0 Byte 1 Byte 2 Byte 3
0x1000
0x1004 X0 X1 X2 X3
0x1008
0x100C Y0 Y1 Y2
0x1010 Y3
Compiler Byte Padding

Compilers have to follow the byte alignment restrictions defined by the target microprocessors. This means that compilers have to add pad bytes into user defined structures so that the structure does not violate any restrictions imposed by the target microprocessor.

Padding does consume memory on cost of performance.

So in Embedded systems where the memory availablity is critical, they do pragma pack again the performance of fetch cycles will be more

Hope it answers all questions... Let me know if anything left out and also if there is any wrong in my explanation.

regards
Prakash

i can give one more additional information along with prakash's explanation. Normally 32 bit mahine have three instructions to read/strore from/to the memory. first instruction will be used to read a byte from the memory. Second and third will be used to read 2 and 4 bytes respectively. below formula applicable for above instructions.

instruction register, memory address ==> memory address must be divisible by the sizeof the data type.

for example,
To read 4 bytes
LA $s,0x0004 ==> correct
LA $s,0x0001==> incorrect
LA $s, 0x0002==> incorrect
LA $s,0x0003==> incorrect
To read 2 bytes
LA $s,0x0004 ==> correct
LA $s,0x0001==> incorrect
LA $s, 0x0002==> correct
LA $s,0x0003==> incorrect

To read a byte
LA $s, any address ==> correct

Note: incorrect statements will create the exception.