CMOS is preffered over NMOS

as CMOS propogates both logic '1', and '0', without a voltage drop

when using NMOS only, logic '1' (i.e Vdd) suffers a thresold drop and the output after passing through one NMOS gate would be Vdd-Vt(thresold voltage of the NMOS gate).

Hence signal margin is very important in NMOS causing possible SI(signal integrity) issues.

Hence CMOS is preferred. By the way CMOS and NMOS and also PMOS are all low powered. Static power consumption is the same, dynamic power consumption depends on signal swing (i.e number of times data line varies)